1. Field of the Invention
The invention disclosed herein relates to a phase compensation circuit and a DC/DC converter using the phase compensation circuit.
2. Description of Related Art
Conventionally, as a power means for various applications, there have been used DC/DC converters (so-called switching power supplies) arranged to generate a desired output voltage from an input voltage by turning on and off an output transistor.
As an example of prior arts related to the above technique, JP 2008-61433 A may be mentioned.
FIG. 15 is a circuit diagram showing a first prior-art example of the DC/DC converter. The DC/DC converter X1 of this prior-art example has a function of, with both an output transistor X11 and a synchronous rectifier transistor X12 turned off in a light-load state (XSLP=L), halting an error amplifier X30, an oscillator X50, a PWM comparator X60, and the like to thereby implement a shifting sleep mode of small power consumption.
Meanwhile, an on-duty Don (i.e., ratio of on-state time Ton of the output transistor X11 occupying in a specified period T) of the DC/DC converter X1 depends on a comparison result between a first voltage VC and a second voltage RAMP both of which are inputted respectively to the PWM comparator X60. Therefore, in the case where the error amplifier X30 that generates the first voltage VC is halted upon a shift to the sleep mode, the on-duty Don of the DC/DC converter X1 becomes unstable, at cancellation of the sleep mode, during a time period until completion of a start-up of the error amplifier X30.
Under such circumstances, the DC/DC converter X1 of this prior-art example has a bias part X80 which holds the first voltage fixed at a proper bias value (equivalent to an initial value of the first voltage VC at the sleep-mode cancellation) during a halt period of the error amplifier X30 in the sleep mode.
However, with the DC/DC converter X1 of this prior-art example, the bias part X80 consumes electric power even in the sleep mode. Thus, there has been room for further improvement in terms of reduction in power consumption.
FIG. 16 is a circuit diagram showing a second prior-art example of the DC/DC converter. The DC/DC converter Y1 of this prior-art example is a step-down type switching power supply of the current mode control method, having a function (so-called OCP (Over Current Protection) function) of restricting coil current IL of a switch output stage Y10 to an upper-limit current value ILMT or less by using a clamper Y110.
FIG. 17 is a COMP versus IL characteristic chart for explaining the OCP function by the clamper Y110. The horizontal axis represents error voltage COMP generated by an error amplifier Y30, and the vertical axis represents average value IL (ave) of the coil current IL.
The clamper Y110 restricts the error voltage COMP to an upper-limit voltage value VLMT or less. As a result, a differential amplifier Y80 is subject to such output feedback control that current sense voltage CSNS responsive to the coil current IL is restricted to the upper-limit voltage value VLMT or less. Thus, the coil current IL is restricted to the upper-limit current value ILMT or less.
In order to suppress a rush current (i.e., excessive coil current IL) arising upon short-circuit emergency of the switch output stage Y10, it is necessary to abruptly change the on-duty Don of the DC/DC converter Y1 (and resultantly the first voltage VC inputted from the differential amplifier Y80 to a PWM comparator Y60 as well) with follow-up after an abrupt change of an output voltage Vo or an input voltage Vi. To meet this demand, it is conceivable to enhance response speed of the differential amplifier Y80 or the clamper Y110 by increasing their drive currents, as an example.
However, there has been a problem that improvidently enhancing the response speed of the the differential amplifier Y80 or the clamper Y110 would cause the voltage loop characteristic to be changed, leading to an increase in oscillation risk.